The present invention relates to transfer control equipment for common use of an input/output bus by individual peripheral units, including a CPU. The equipment further controls the transfer of information between two common input/output buses, each of which has an individual "use right" in a data processing system.
A first conventional system for transferring information from one common bus to another will store data from a first common bus in a common memory connected between the two buses by a single path. The system will read the data from the common memory and transfer the data to a second common bus. The entire transfer operation is under control of a CPU connected to one of the buses. This system is not desirable since the CPU must interrupt its processing in order to accomplish this transfer.
In a second conventional system, the two common input/output buses are connected by individual connecting equipment, which replaces the common memory of the first conventional system. In this embodiment, data to be transferred from a first common bus is temporarily stored by a local memory unit attached to that bus. Then, the data is transferred from the local memory to the connecting equipment, via the connecting bus, to the second common bus. If a significant quantity of data is transferred, the first bus is occupied a substantial amount of time, so that the efficiency of the use of the bus and the performance of the CPU connected to the first bus are decreased.
A problem with data transfer on any common bus is conflict between the transfer request from one unit and the transfer request from another unit. To solve the problem, in the second conventional unit, the bus connecting equipment will receive and store the entire block of information to be transferred and will terminate the use of the bus. Clearly, the bus connecting equipment must have a memory large enough to store the content of bus transfer and an increase in the amount of data to be transferred requires a larger memory. Moreover, if there are several such memories, on the occurrence of malfunction, the recovery process becomes more complex.
In the second conventional unit, when the bus connecting equipment receives a transfer from a unit on the first bus, including the address of the destination unit, the original CPU initially determines by a comparison process whether there is a unit having an identical address that is connected to the second common bus. If there is a unit with the identical address, a bus use request signal is sent to the second common bus. Such a transfer control system is disclosed in U.S. Pat. No. 4,234,919. In the system described in that patent, the address of the destination unit is generated by a unit on the first common bus, is stored in the local memory and is compared. If the comparison is positive, then the address is sent from the local unit to the second common bus. However, if a new unit is connected to the second common bus, or if a unit connected to the second bus is changed or deleted, the content of the memory must be changed.